1. Technical Field
This invention relates generally to Metal-Insulator-Metal devices, and more particularly, to an approach for avoiding undesired reduction of the insulating layer thereof.
2. Background Art
FIG. 1 illustrates a two-terminal metal-insulator-metal (MIM) resistive memory device 30. The memory device 30 includes a metal, for example copper electrode 32, an active insulating layer 34, for example copper oxide on and in contact with the electrode 32 (or a multilayer oxide stack if so chosen), and a metal, for example copper electrode 36 on and in contact with the active layer 34 (the electrodes may be of different materials if chosen). With reference to FIG. 5, initially, assuming that the memory device 30 is unprogrammed, in order to program the memory device 30, ground is applied to the electrode 32, while a positive voltage is applied to electrode 36, so that an electrical potential Vpg (the “programming” electrical potential) is applied across the memory device 30 from a higher to a lower electrical potential in the direction from electrode 36 to electrode 32. Upon removal of such potential the memory device 30 remains in a conductive or low-resistance state having an ON-state resistance.
In the read step of the memory device 30 in its programmed (conductive) state, an electrical potential Vr (the “read” electrical potential) is applied across the memory device 30 from a higher to a lower electrical potential in the direction from electrode 36 to electrode 32. This electrical potential is less than the electrical potential Vpg applied across the memory device 30 for programming (see above). In this situation, the memory device 30 will readily conduct current, which indicates that the memory device 30 is in its programmed state.
In order to erase the memory device 30, a positive voltage is applied to the electrode 32, while the electrode 36 is held at ground, so that an electrical potential Ver (the “erase” electrical potential) is applied across the memory device 30 from a higher to a lower electrical potential in the direction of from electrode 32 to electrode 36. Depending on the embodiment, the memory device 30 may be erased by applying an electrical potential across the memory device from higher to lower potential in the direction from the electrode 36 to the electrode 32, i.e., the same direction as the programming potential.
In the read step of the memory device 30 in its erased (substantially non-conductive) state, the electrical potential Vr is again applied across the memory device 30 from a higher to a lower electrical potential in the direction from electrode 36 to electrode 32 as described above. With the active layer 34 (and memory device 30) in a high-resistance or substantially non-conductive OFF state, the memory device 30 will not conduct significant current, which indicates that the memory device 30 is in its erased state.
The insulating layer typically takes the form of a thin oxide layer film (for example copper oxide, CuOx, described above) or a stack of multilayer multiple thin oxide films. Many of these oxide films have low free energy of formation and thus may be readily reduced by H2. This H2 may arise as a by-product in process steps that follow the formation of the MIM stack, or may be released from ILD (Interlayer Dielectric) or passivation silicon nitride (both of which are excellent reservoirs of hydrogen), during a high temperature thermal cycle. This undesired reduction of the oxide layer(s) results in degradation thereof, in turn causing degradation in performance of the resulting device.
Therefore, what is needed is an approach where ambient H2 is kept from attacking the oxide film(s), so that undesired reduction of thereof is avoided.